Senior RTL Design Engineer for High-Performance SoCs

Analog Devices, Inc.; Limerick; Hybrid; EUR 90,000 - 120,000; Full time

Job summary

Analog Devices, Inc. in Limerick, Ireland, is seeking a Senior Digital Design Engineer to develop and verify RTL for digital blocks in mixed-signal SoCs.

You will work with cross‑functional teams to ensure timing closure, enable DFT insertion, and support silicon bring‑up in a fast paced, agile environment. The ideal candidate has 4+ years in ASIC/SoC digital design, strong Verilog/SystemVerilog skills, and experience with Genus/Innovus flows, Python or C scripting, and basic lab practices.

Qualifications

• BS in Electrical or Computer Engineering or equivalent.
• 4+ years of ASIC/SoC digital design experience.
• Proficiency in Verilog/SystemVerilog and scripting languages (Python, C).
• Familiarity with RTL-to-GDS flows (Genus, Innovus, Tempus, Conformal).
• Understanding of DFT concepts and basic test strategies.
• Working knowledge of analog circuit operation and lab practices.
• Strong problem-solving and independent working ability.
• Good organization and communication skills.

Responsibilities

• Develop and verify RTL for digital blocks and subsystems; ensure functional correctness and timing closure.
• Synthesize and perform static timing analysis; support DFT insertion and pattern generation.
• Collaborate with analog, firmware and validation teams to integrate digital content into mixed-signal SoCs.
• Assist with silicon bring-up and debug; support lab measurements and correlation to simulation.
• Contribute to methodology improvements and automation initiatives.

Skills

Verilog/SystemVerilog

Python

C

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Genus

Innovus

Tempus

Conformal

Job description

Analog Devices, Inc. in Limerick, Ireland, is seeking a Senior Digital Design Engineer to develop and verify RTL for digital blocks in mixed-signal SoCs.

You will work with cross‑functional teams to ensure timing closure, enable DFT insertion, and support silicon bring‑up in a fast paced, agile environment. The ideal candidate has 4+ years in ASIC/SoC digital design, strong Verilog/SystemVerilog skills, and experience with Genus/Innovus flows, Python or C scripting, and basic lab practices.