Senior ASIC Verification Engineer - UVM & SystemVerilog

European Tech Recruit; Munster; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit is collaborating with a leading semiconductor company in the Cork area seeking a Senior Design Verification Engineer to join the team. You will apply cutting-edge verification methodologies, develop testbenches, verify RTL sensor algorithms, and collaborate with design and systems engineers to validate designs.

The role requires 3+ years in ASIC verification, UVM-based approaches, and proficiency in SystemVerilog and shell scripting.

Qualifications

• Bachelor's degree required in science or engineering.
• Minimum 3 years of experience in ASIC design verification or related role.
• Experience with gate-level simulation debugging and power extraction tools is an advantage.
• Strong experience building constrained-random verification environments using UVM and coverage-driven verification.
• Extensive experience using RTL simulation tools.
• Proficiency in UVM, SystemVerilog, and shell scripting (Perl/Python).
• Familiarity with C/C++ is a plus.
• Debugging experience.
• Experience with formal verification tools a bonus.
• Familiarity with SystemC and Matlab is a bonus.

Responsibilities

• Apply verification methodologies including UVM and Formal Verification.
• Develop and maintain testbenches and verification components (UVCs, C models).
• Verify RTL of sensor algorithms to meet ASIC tapeout quality standards.
• Create test plans based on design specs and collaborate with design/system engineers.
• Integrate C models into the UVM framework for verification efficiency.
• Write and maintain SystemVerilog assertions.
• Perform debugging, verification, optimization, and bit-exact testing with test vectors.
• Support integration of designs into higher level subsystems, including test planning and debugging.
• Use Python automation to streamline workflows.
• Document all verification activities and methodologies.

Skills

UVM-based functional verification

Constrained-random verification

SystemVerilog

Shell scripting (Perl/Python)

Education

Bachelor's degree in Science or Engineering

Tools

RTL simulation tools

UVCs and C models

C/C++

SystemC

Job description

European Tech Recruit is collaborating with a leading semiconductor company in the Cork area seeking a Senior Design Verification Engineer to join the team. You will apply cutting-edge verification methodologies, develop testbenches, verify RTL sensor algorithms, and collaborate with design and systems engineers to validate designs.

The role requires 3+ years in ASIC verification, UVM-based approaches, and proficiency in SystemVerilog and shell scripting.