Lead Analog Layout Engineer for 64Gbps SERDES

Cadence; Cork; On-site; EUR 90,000 - 140,000; Full time

Job summary

Cadence in Cork, Ireland is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within a SERDES product line. You will drive high-speed analog layouts and guide a global team across time zones.

The role requires 7+ years in CMOS SERDES layout, proficiency with Cadence tools, and strong collaboration skills. You will influence design quality from floorplanning through final verification while coordinating with circuit designers and

Qualifications

• 7+ years of CMOS SERDES/high-speed I/O layout experience.
• Proficient in analog/mixed-signal layout and back-end flows.
• Strong problem solving and communication skills.
• Experience coordinating with global teams.
• Degree in EE or related field required.

Responsibilities

• Design high-speed SERDES for UCIe products up to 64 Gbps.
• Create high-quality analog/mixed-signal layouts with layout teams.
• Lead back-end flow from floorplanning to verification.
• Provide technical leadership within the team.
• Collaborate with global Cadence teams across time zones.

Skills

CMOS SerDES

High-speed layout

Technical leadership

Team collaboration

Education

BEng/MEng/PhD in Electrical Engineering

Tools

Cadence tools

Wafer-level layout

Job description

Cadence in Cork, Ireland is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within a SERDES product line. You will drive high-speed analog layouts and guide a global team across time zones.

The role requires 7+ years in CMOS SERDES layout, proficiency with Cadence tools, and strong collaboration skills. You will influence design quality from floorplanning through final verification while coordinating with circuit designers and