Lead Analog Layout Design Engineer (SerDes)

Cadence Design Systems; Cork; On-site; EUR 110,000 - 170,000; Full time

Job summary

Cadence Ireland in Cork is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within the SERDES Product Team.

You will design high speed SERDES up to 64 Gbps on cutting-edge nodes, collaborate with circuit designers worldwide, and guide the back-end flow from floorplanning to final sign-off.

The role requires 7+ years in CMOS SERDES layout and a strong track record delivering IP and test chips, with a degree in engineering.

Qualifications

• Minimum of 7 years CMOS SERDES or high-speed I/O layout experience.
• Proficient with SERDES blocks: Driver, Receiver, Serializer/Deserializer, PLL.
• Experience delivering IP and test chips with clean flows.
• Collaborates with global teams and engineers across time zones.
• Educational background: BEng/MEng or PhD.

Responsibilities

• Design high-speed SERDES for UCIe products at up to 64 Gbps.
• Create high-quality analog/mixed-signal layouts with foundry rules.
• Lead back-end flow from floorplanning to verification.
• Provide technical leadership on layout design from block to PHY level.
• Coordinate with global teams across US and Ireland time zones.

Skills

CMOS SERDES experience

Analog/mixed-signal design

High-speed I/O understanding

Communication skills

Team collaboration

Problem-solving

Education

BEng, MEng or PhD

Tools

Cadence tool experience

Cadence Virtuoso

PVS (Cadence)

Layout verification tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title

Lead Analog Layout Design Engineer (SERDES/UCie)

Location

Cork

Reports to

Sr Principal Engineer

Job Overview

The Lead Analog Layout Design Engineer will take a Technical Leadership role on the PMA custom layout design team as part of a SERDES Product Team at Cadence Ireland.

Job Responsibilities

• Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET CMOS)
• Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers
• Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
• Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications

• Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
• Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Working with custom layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

Additional Skills/Preferences

• Cadence tool experience and design experience at >10Gbps and in <16nm technologies
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools
• Interest in bringing changes to the analog/custom layout design paradigm

Additional Information

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Equal Opportunity Employer Statement

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.