Lead Analog Layout Engineer for 64 Gbps SERDES (UCie)

Cadence Design Systems; Cork; On-site; EUR 110,000 - 170,000; Full time

Job summary

Cadence Ireland in Cork is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within the SERDES Product Team.

You will design high speed SERDES up to 64 Gbps on cutting-edge nodes, collaborate with circuit designers worldwide, and guide the back-end flow from floorplanning to final sign-off.

The role requires 7+ years in CMOS SERDES layout and a strong track record delivering IP and test chips, with a degree in engineering.

Qualifications

• Minimum of 7 years CMOS SERDES or high-speed I/O layout experience.
• Proficient with SERDES blocks: Driver, Receiver, Serializer/Deserializer, PLL.
• Experience delivering IP and test chips with clean flows.
• Collaborates with global teams and engineers across time zones.
• Educational background: BEng/MEng or PhD.

Responsibilities

• Design high-speed SERDES for UCIe products at up to 64 Gbps.
• Create high-quality analog/mixed-signal layouts with foundry rules.
• Lead back-end flow from floorplanning to verification.
• Provide technical leadership on layout design from block to PHY level.
• Coordinate with global teams across US and Ireland time zones.

Skills

CMOS SERDES experience

Analog/mixed-signal design

High-speed I/O understanding

Communication skills

Team collaboration

Problem-solving

Education

BEng, MEng or PhD

Tools

Cadence tool experience

Cadence Virtuoso

PVS (Cadence)

Layout verification tools

Job description

Cadence Ireland in Cork is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within the SERDES Product Team.

You will design high speed SERDES up to 64 Gbps on cutting-edge nodes, collaborate with circuit designers worldwide, and guide the back-end flow from floorplanning to final sign-off.

The role requires 7+ years in CMOS SERDES layout and a strong track record delivering IP and test chips, with a degree in engineering.