Lead Analog Layout Design Engineer (SerDes)

Cadence; Cork; On-site; EUR 90,000 - 140,000; Full time

Job summary

Cadence in Cork, Ireland is seeking a Lead Analog Layout Design Engineer to take a technical leadership role on the PMA custom layout design team within a SERDES product line. You will drive high-speed analog layouts and guide a global team across time zones.

The role requires 7+ years in CMOS SERDES layout, proficiency with Cadence tools, and strong collaboration skills. You will influence design quality from floorplanning through final verification while coordinating with circuit designers and

Qualifications

• 7+ years of CMOS SERDES/high-speed I/O layout experience.
• Proficient in analog/mixed-signal layout and back-end flows.
• Strong problem solving and communication skills.
• Experience coordinating with global teams.
• Degree in EE or related field required.

Responsibilities

• Design high-speed SERDES for UCIe products up to 64 Gbps.
• Create high-quality analog/mixed-signal layouts with layout teams.
• Lead back-end flow from floorplanning to verification.
• Provide technical leadership within the team.
• Collaborate with global Cadence teams across time zones.

Skills

CMOS SerDES

High-speed layout

Technical leadership

Team collaboration

Education

BEng/MEng/PhD in Electrical Engineering

Tools

Cadence tools

Wafer-level layout

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title

Lead Analog Layout Design Engineer (SERDES/UCie)

Location

Cork

Reports to

Sr Principal Engineer

Job Overview

The Lead Analog Layout Design Engineer will take a Technical Leadership role on the PMA custom layout design team as part of a SERDES Product Team at Cadence Ireland.

Job Responsibilities

• Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET CMOS)
• Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers
• Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
• Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications

• Candidate's background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
• Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Working with custom layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

Skills

Additional Skills/Preferences

• Cadence tool experience and design experience at >10Gbps and in
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools
• Interest in bringing changes to the analog/custom layout design paradigm

Additional Information

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel

>10%

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