Lead Analog Layout Design Engineer

Cadence Design Systems; Cork; On-site; EUR 110,000 - 160,000; Full time

Job summary

Cadence Design Systems in Cork seeks a Lead Analog Layout Design Engineer (SERDES/UCie) to drive technical leadership on the PMA custom layout team within the SERDES Product Team. The role focuses on high-speed SERDES design up to 64 Gbps, working with global teams and leveraging Cadence tools on cutting-edge technology nodes.

Ideal candidates bring 7+ years in CMOS SERDES or high-speed I/O layout, with strong analog/layout expertise, and a PhD/MEng/BEng.

Qualifications

• Minimum 7 years of CMOS SERDES or high-speed I/O IC layout experience.
• Proficient in SERDES blocks: Driver, Receiver, Serializer, Deserializer, PLL, clock distribution, biasing, regulators.
• Experience implementing high-speed cells with quality and efficiency.
• Collaborating with global layout and circuit teams to deliver IP and test chips.
• Excellent problem-solving, analog aptitude, and communication; able to work with teams worldwide.
• BEng, MEng or PhD.

Responsibilities

• Design of High Speed SERDES for UCIe products up to 64 Gbps on advanced nodes (e.g. 2nm).
• Create high-quality analog/mixed-signal layouts in collaboration with circuit designers.
• Lead back-end flow from floor planning to layout verification against foundry rules.
• Provide technical leadership on layout design from block to PHY top level.
• Coordinate with global teams in different time zones.

Skills

CMOS SERDES

High-speed I/O layout

Analog layout

Global collaboration

Problem solving & communication

Education

BEng/MEng/PhD

Tools

Cadence tools

Virtuoso

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title

Lead Analog Layout Design Engineer (SERDES/UCie)

Location

Cork

Reports to

Sr Principal Engineer

Job Overview

The Lead Analog Layout Design Engineer will take a Technical Leadership role on the PMA custom layout design team as part of a SERDES Product Team at Cadence Ireland.

Job Responsibilities

• Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET CMOS)
• Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers
• Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
• Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications

• Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
• Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Working with custom layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

Additional Skills/Preferences

• Cadence tool experience and design experience at >10Gbps and in <16nm technologies
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools
• Interest in bringing changes to the analog/custom layout design paradigm

Additional Information

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.

We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

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