Lead Analog Layout Architect for High-Speed SERDES 64Gbps

Cadence Design Systems

Cork

On-site

EUR 110,000 - 160,000

Full time

9 days ago

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Job summary

Cadence Design Systems in Cork seeks a Lead Analog Layout Design Engineer (SERDES/UCie) to drive technical leadership on the PMA custom layout team within the SERDES Product Team. The role focuses on high-speed SERDES design up to 64 Gbps, working with global teams and leveraging Cadence tools on cutting-edge technology nodes.

Ideal candidates bring 7+ years in CMOS SERDES or high-speed I/O layout, with strong analog/layout expertise, and a PhD/MEng/BEng.

Qualifications

Minimum 7 years of CMOS SERDES or high-speed I/O IC layout experience.
Proficient in SERDES blocks: Driver, Receiver, Serializer, Deserializer, PLL, clock distribution, biasing, regulators.
Experience implementing high-speed cells with quality and efficiency.
Collaborating with global layout and circuit teams to deliver IP and test chips.
Excellent problem-solving, analog aptitude, and communication; able to work with teams worldwide.
BEng, MEng or PhD.

Responsibilities

Design of High Speed SERDES for UCIe products up to 64 Gbps on advanced nodes (e.g. 2nm).
Create high-quality analog/mixed-signal layouts in collaboration with circuit designers.
Lead back-end flow from floor planning to layout verification against foundry rules.
Provide technical leadership on layout design from block to PHY top level.
Coordinate with global teams in different time zones.