Senior Layout Designer

Software Placements; Cork; On-site; EUR 90,000 - 150,000; Full time

Job summary

Software Placements in Cork, Ireland, operates with a leading multinational semiconductor client seeking a Senior AMS Layout Design Engineer. The role is based in Cork City and requires onsite presence four days per week.

The candidate will take a technical leadership role on the PMA/PCS SERDES/UCIe layout team, collaborating with circuit designers and global teams to deliver high-speed layouts up to 112 Gbps and beyond.

Qualifications

• 7+ years of CMOS SERDES/high-speed I/O layout design experience.
• Expertise in Driver/Receiver/Serializer/Deserializer blocks and PHY gds.
• Experience with PMA/PCS hierarchies and clock/power distribution.
• Collaboration with global design teams and project managers

Responsibilities

• Lead layout design on the PMA/PCS team for SERDES/UCIe products.
• Design high-quality layouts and ensure conformance to foundry DRCs.
• Oversee back-end flow from floorplanning to final verification.
• Coordinate with global teams across time zones

Skills

CMOS SERDES layout

High-speed I/O design

Cadence tools

Team collaboration

Problem solving

Education

BEng/MEng/PhD

Tools

Cadence

Virtuoso

PVS

Job description

Our client a leading Multinational Semiconductor Company requires Senior AMS Layout Design Engineer for role based in Cork City, Ireland.

You will be required to be onsite 4 days per week.

Role:

You will take a Technical Leadership role on the PMA custom layout design team as part of a SERDES/UCIe Product Team in Cork, Ireland.

Responsibilities:

• Design of High Speed SERDES/UCIe products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design quality layouts of Analog/Mixed-Signal circuit blocks, working in collaboration with circuit designers
• Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
• Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off
• Work with global teams (US, west coast and east coast), which work in different time-zones

Experience:

• A minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
• Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Architecture and implementation of complete PHY gds with integration of PMA, PCS hierarchies and optimized clock and power distribution strategies
• Working with custom layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment

Education:

• BEng, MEng or PhD

Additional Skills/Preferences:

• Cadence tool experience and design experience at >10Gbps and in <40nm technologies
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools
• Interest in bringing changes to the analog/custom layout design paradigm

Contact:

For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email [e-mail]