Design Verification Manager

Software Placements; Cork; On-site; EUR 120,000 - 180,000; Full time

Job summary

Software Placements seeks a seasoned Digital Design Verification Manager to lead the verification of complex ASIC/SoC designs. The role is based onsite in Ireland (Limerick or Cork) with a minimum of three days per week on site.

You will drive verification strategy, manage a cross-functional team, and ensure coverage-driven verification meets tape-out readiness. The ideal candidate has 10+ years in engineering with HW/SW verification, is proficient in SystemVerilog/UVM, constrained-random

Qualifications

• PhD or degree in Electronic Engineering or equivalent.
• Minimum 5 years managing digital design verification teams.
• 10+ years in engineering with HW/SW verification flows.
• Strong experience with SystemVerilog/UVM and coverage-driven verification.

Responsibilities

• Define verification strategy, plans, milestones.
• Lead and mentor verification engineers across projects.
• Oversee testbench development and ensure coverage goals.
• Coordinate cross-functional teams (RTL, firmware, emulation).
• Track progress, risks, and formal/informal verification activities.
• Promote automation and reusable verification environments.

Skills

Leadership

Verification management

SystemVerilog/UVM

Constrained-random

Coverage-driven

Mentoring

Education

PhD or degree in Electronic Engineering

Tools

vManager

vPlan

Regression tools

Job description

Client:

Our client a leading Multinational Semiconductor Company requires Digital Design Verification Manager for role in Limerick or Cork, Ireland. The role requires the candidate to be onsite a minimum of 3 days per week.

Role:

You will be responsible for leading the verification of digital/ASIC/SoC designs and ensuring the chip meets its functional specifications before tape-out.

Responsibilities:

Verification strategy:

• Define the overall verification methodology, plan, and milestones.
• Develop verification plans from design specifications and requirements.
• Establish coverage goals and sign-off criteria.

Team management:

• Lead and mentor verification engineers.
• Allocate engineers to projects and verification areas.
• Review performance, development needs, and technical growth.
• Coordinate work across multiple verification teams.

Verification execution:

• Oversee development of SystemVerilog/UVM testbenches, tests, assertions, and coverage.
• Ensure verification environments are reusable, scalable, and maintainable.
• Track simulation, regression, coverage, and bug status.
• Ensure functional, code, assertion, and coverage targets are achieved.

Debug and quality:

• Drive root-cause analysis of design and verification failures.
• Review critical bugs and determine appropriate priorities.
• Monitor verification quality and identify gaps before tape-out.
• Establish processes for reducing escapes and improving verification efficiency.

Cross-functional collaboration:

• Work closely with RTL/design, architecture, firmware/software, emulation, FPGA, physical design, and validation teams.
• Resolve specification ambiguities with architects and designers.
• Coordinate verification dependencies across IPs and SoCs.

Project management:

• Create schedules, estimate resources, and track deliverables.
• Manage verification risks, dependencies, and technical blockers.
• Report progress, coverage, bugs, and risks to senior management.
• Support tape-out readiness reviews.

Technical leadership:

• Select verification methodologies and tools.
• Promote automation, constrained-random testing, formal verification, and coverage-driven verification where appropriate.
• Evaluate new verification technologies and improve team productivity.

Education:

• PhD, post-graduate or degree qualification in Electronic Engineering or similar.

Experience:

• 5 years Digital Design Verification Management
• 10+ years’ relevant engineering experience.
• Experience of full-product verification flows, including HW & FW.
• Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
• Experienced with Assertions like System Verilog Assertions
• Experience with vManager, vPlan and Regressions, etc.
• Experience working on mixed-signal ICs is a plus.
• Experience with debugging test failures and report verification result to achieve the expected functional/code coverage goals
• Extensive usage of RTL simulation tools.
• UVM, System Verilog, Perl/Python shell-scripting skills required
• Excellent interpersonal and communications skills.
• The ability to work with cross-functional teams.
• The ability to support and mentor less experienced team members

Contact:

For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email [e-mail]