Principal Digital Design Verification Engineer

Software Placements; Cork; On-site; EUR 120,000 - 160,000; Full time

Job summary

Software Placements is recruiting a Principal Digital Design Verification Engineer for a Cork City, Ireland role with a leading semiconductor EDA provider. You will verify IP blocks, focusing on DDR memory controller architectures and MDV methodologies.

You will architect verification environments, develop UVM-SV scoreboards, functional coverage, and assertions. Collaboration across design and support teams is essential for productivity and quality improvements.

Qualifications

• Degree in Electrical/Electronic Engineering or Microelectronics.
• 10–15 years in microelectronics/EDA is required.
• Experience with SystemVerilog Constrained Random verification essential.
• Excellent written and spoken English essential.

Responsibilities

• Architect verification environments for IP such as Ethernet, CXL, Storage.
• Develop UVM-SV scoreboards for self-checking regressions.
• Create functional coverage as part of MDV environments.
• Develop SystemVerilog Assertions for Formal and Simulation.
• Define and manage verification plans (vPlans) with Cadence vManager.
• Build automated regression environments, e.g., Jenkins.
• Participate in technical reviews and ISO-9001 checklist reviews.
• Collaborate with design engineers to debug complex tests.
• Improve quality and efficiency via automation and better methods.
• Work across Design, Support, Delivery, Applications, PHY teams.

Skills

MDV

SystemVerilog

Verifications

English

Education

Electrical/Electronic Engineering or Microelectronics

Tools

Cadence vManager

Jenkins

UVM-SV

Job description

Client:

Our client a leading Multinational Semiconductor EDA provider require Principal Digital Design Verification Engineer (MDV) for role based in Cork City, Ireland.

Role:

You will be involved in Design Verification of Intellectual Property (IP) for a variety of High-Tech Markets. This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI.

The Principal Digital Design Verification Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India.

Responsibilities:

• Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage.
• Development of UVM-SV Scoreboards for self-checking regressions.
• Development of Functional Coverage as part of Metric Driven Verification Environments.
• Development of SystemVerilog Assertions for use in Formal and Simulation Environments.
• Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
• Creation and Management of Automated Regression Environments, e.g. Jenkins.
• Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
• Close Collaboration with Design Engineers to debug complex test scenarios.
• Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.
• Work across disciplines with Design, Support, Delivery, Application Engineers, PHY team, etc.

Qualifications:

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.

Experience:

• 10-15 years’ experience in microelectronics/EDA industry.
• Experience of SystemVerilog Constrained Random Verification essential.
• Experience of Metric Driven Verification (MDV) essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal, and communication skills.

Additional Skills/Preferences:

• Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred.
• Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
• AXI and/or CHI-E experience is highly desirable.