Computer Aided Design Engineer

European Tech Recruit; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

European Tech Recruit has an opening for a Staff CAD Engineer to join its Graphics team, contributing to next-generation GPU technology. This role focuses on RTL-to-GDSII flow, developing advanced silicon design methodologies and PPA improvements across GPU cores.

You will collaborate with graphics microarchitecture, design, and implementation teams, applying Verilog/SystemVerilog expertise and using Synopsys tools to optimise power, performance, and area while delivering high-quality results.

Qualifications

• Proficient in Verilog and SystemVerilog for RTL design.
• Experience with RTL-to-GDSII flow and ASIC verification.
• Ability to optimize PPA across GPU cores and manage power, timing, and area trade-offs.
• Scripting skills in UNIX shell, Python, Perl or TCL.

Responsibilities

• Implement and deliver GPU cores RTL through to GDSII.
• Develop semi-custom design flows and methodologies.
• Identify opportunities to improve existing flows and processes.
• Collaborate with graphics microarchitecture, design and implementation teams to drive PPA improvements.

Skills

Verilog / SystemVerilog

RTL design

PPA optimisation

Scripting (Python/Perl/TCL)

Education

Bachelor's degree in Computer Engineering, CS, or Electrical Engineering

Master's degree preferred

Tools

Synopsys Fusion Compiler

RTL Architect

PrimePower

PrimeTime

Prime Closure

GDSII

Job description

A global leader in semiconductor technology is looking for an experienced Staff CAD Engineer to join its Graphics team, contributing to the development of next-generation GPU technology.

This is an opportunity to work on advanced silicon designs, developing innovative flows, methodologies, and algorithms to optimise power, performance, and area (PPA) across cutting-edge GPU cores.

You will collaborate closely with graphics microarchitecture, design, and implementation teams, helping drive improvements across the full ASIC development lifecycle.

The role requires a fundamental understanding of RTL design and the ASIC development flow from RTL to GDS, including synthesis, static timing analysis, formal verification, physical design, and ECO generation and verification. You will collaborate with design, technology, power, implementation, sign-off, and post-silicon teams to drive PPA improvements across GPU cores.

Key Skills and Experience

Experience in the following areas would be highly advantageous:

• Implementation and delivery of GPU cores from RTL through to GDSII.
• Development of semi-custom design flows and methodologies.
• Identifying opportunities to improve existing flows and processes.
• Proficiency in Verilog and SystemVerilog.
• RTL synthesis using physically aware tools.
• Managing design constraints relating to power, timing, clocking, and interfaces.
• Formal verification for RTL-to-netlist and netlist-to-netlist checks.
• Clock tree analysis and optimisation.
• ECO methodologies for functional and timing fixes.
• Managing design targets and trade-offs across power, performance, and area (PPA).

Preferred Qualifications

• 5-7 years of experience developing methodologies to improve PPA.
• Fundamental understanding of digital design and RTL development.
• Hands-on experience with EDA tools such as Synopsys Fusion Compiler, RTL Architect, PrimePower, PrimeTime, and Prime Closure.
• Experience developing scripts using UNIX Shell, Python, Perl, and/or TCL.
• Strong analytical and interpersonal skills, with the ability to work independently.
• A highly motivated, collaborative approach, with a strong focus on deliverable quality and customer requirements.

Education Requirements

• Required: Bachelor's degree in Computer Engineering, Computer Science, or Electrical Engineering.
• Preferred: Master's degree in Computer Engineering, Computer Science, or Electrical Engineering.