Static Timing Analysis Engineer - (Graphics / STA / Semiconductors) - Visas Supported

European Tech Recruit; Ireland; On-site; EUR 90,000 - 120,000; Full time

Job summary

Global Semiconductor Company in Cork, Ireland seeks an experienced GPU STA Engineer to join the GPU STA Team. You will evaluate block-level and top-level timing to ensure high performance and power efficiency in advanced GPUs.

You will contribute to chip signoff methodology, automate timing/data processes, and drive project goals with production support, ensuring timely delivery in a fast-paced semiconductor environment.

Qualifications

• Master's or Bachelor's degree in Computer Engineering or Electrical Engineering.
• 3+ years industrial work experience.
• Expertise in Primetime, Primeshield and Tempus based, hierarchical analysis for large SoCs.
• Expertise in Redhawk SC for flow development of static/dynamic/DVD.
• Hands on Tweaker, Tempus ECO and PTECO for timing closure.
• Highly proficient in Python, TCL and Perl.
• Excellent problem-solving skills and results-driven in a fast-paced environment.
• Good communication skills in a multi-disciplinary setting.

Responsibilities

• Enhancing STA and PDN/Timing technologies for design closure in low power architectures.
• Drive accuracy of timing closure and static/dynamic flows to reduce turnaround time.
• Automation for timing and power data mining and processing.
• Participate in project proposals with milestones and deliverables.
• Execute and deliver project goals with production support.
• Resolve issues across development phases for smooth execution.

Skills

Python

TCL

Perl

Problem-solving

Communication

Education

Master's/Bachelor's in Computer or Electrical Engineering

Bachelor's in Computer or Electrical Engineering

Tools

Primetime

Primeshield

Tempus

Redhawk SC

Tempus ECO

PTECO

Job description

GPU STA Engineer

A fantastic opportunity for an experienced GPU Engineer to join a leading Global Semiconductor Company, working alongside their GPU STA Team in Cork, Ireland.

You will work alongside a team responsible for evaluating block-level and top-level timing to ensure optimal performance and power efficiency in advanced GPUs. Your role will be crucial in developing high-performance, low-power graphics solutions that drive the future of technology.

Responsibilities:

You will be member of team developing chip signoff methodology and flow:

• Enhancing STA and PDN / Timing technologies for design closure methodology with unique challenges driven by Low power architecture, Si Variation, Low voltage operation and other challenges.


• Driving accuracy of timing closure and static/dynamic flows to reduce turn around time


• Automation for timing and power data mining and processing


• Participating in project proposal development including key milestones and deliverables


• Executing and deliver project goals in a timely manner with production support


• Resolving issues in all phases of development to assure smooth project execution

Good to have:

• Master's/Bachelors of Computer Engineering or Electrical Engineering


• 3+ years industrial work experience.


• Expertise in Primetime, Primeshield and Tempus based, hierarchical analysis for large SoCs


• Expertise in Redhawk SC for flow development of static/dynamic/DVD


• Hands on Tweaker, Tempus ECO and PTECO for timing closure


• Highly Proficient in Python, TCL and Perl


• Excellent problem-solving skills and results-driven, able to work and drive practical solutions under research environment.


• Good communication skill and personal skills in a multi-disciplinary, fast-paced engineering environment

By applying to this role, you understand that we may collect your personal data & store & process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/wp-content/uploads/2020/04/Privacy-Notice.pdf).