Digital ASIC Design Engineer

European Tech Recruit; Cork; On-site; EUR 65,000 - 90,000; Full time

Job summary

Unknown Semiconductor Company in Ireland is seeking a Digital ASIC Engineer to join the design team to develop digital blocks used in consumer electronics, wearables and connected devices. You will write specs, code RTL in SystemVerilog, verify with testbenches, perform synthesis and timing closure, and help shape low-power design choices while collaborating with architects and other HW/SW engineers.

You will also script in Python to speed up team processes and communicate effectively in a

Qualifications

• Proven RTL design experience in a professional setting.
• Strong SystemVerilog coding and verification skills.
• Experience with Python or Tcl/Perl scripting for automation.
• Clear communicator and team player.

Responsibilities

• Design and code digital logic blocks for chip integration.
• Verify against test benches and fix defects.
• Handle synthesis and timing closure using signoff tools.
• Collaborate with systems architects and HW/SW engineers.
• Support power budgeting and low-power design decisions.

Skills

RTL Design

SystemVerilog

Python scripting

C++/SystemC

Tools

Synthesis tools (Cadence/Synopsys)

PrimeTime/PTPX

LEC

Signoff tools

Job description

Our client, a well-established semiconductor business supplying chip IP into consumer electronics, is looking to add a Digital ASIC Engineer to their design team. The role sits within a group responsible for custom digital blocks that end up inside phones, wearables, connected vehicles and other everyday hardware.

You'll be involved end-to-end: writing specs, coding and verifying RTL, running synthesis, and handing off clean, timing-closed netlists ready for layout. It's a genuinely collaborative role, you'll be working alongside systems architects and other hardware/software engineers to get digital blocks integrated cleanly into larger chip designs.

Day to day, you'll be:

• Designing and coding digital logic blocks destined for chip integration
• Verifying designs against test benches, chasing down and fixing bugs
• Handling synthesis and timing closure work using standard EDA signoff tools
• Looking at power budgets and helping shape low-power design choices
• Writing scripts/tooling (Python) to speed up team processes
• Working with other engineering functions and supporting release governance

On paper, we'd like to see:

• Solid RTL Design experinece as well as comfortable in SystemVerilog, plus scripting (Python/Tcl/Perl)
• 2+ years of Digital TRL Design experience in a professional setting
• Solid tooling exposure; synthesis, LEC, PrimeTime/PTPX or similar signoff tools
• Nice to have: ECO experience, DRC/CDC checks, C++/SystemC, DFT/MBIST exposure
• A clear communicator who's happy working at pace in a team setting