Physical Design Implementation

European Tech Recruit; Cork; On-site; EUR 90,000 - 135,000; Full time

Job summary

European Tech Recruit in Cork, Ireland, is seeking a Senior Physical Design Implementation Engineer to join a global semiconductor team. You will work on the end-to-end PD flow, from netlist handoff to GDS, including floorplanning, power planning, placement, CTS, and routing.

The ideal candidate has 4+ years of hands-on PD experience with 10nm and below, solid STA and timing-closure knowledge, power-integrity skills, and familiarity with DRC-clean layouts and physical verification.

Qualifications

• 4+ years of hands-on Physical Design experience.
• Full PD lifecycle knowledge from netlist to GDS.
• STA concepts, timing-closure strategies, and congestion awareness.
• Power analysis and power-integrity evaluation knowledge.
• Knowledge of PD verification flows and DRC-clean layouts.

Responsibilities

• Lead floorplanning, placement, CTS, routing optimizations.
• Ensure DRC-clean layouts and power integrity in designs.

Skills

Physical Design

Placement & Routing

STA & Timing Closure

Power Integrity

Floorplanning

Netlist to GDS

Tools

Cadence

Synopsys

GDSII

Job description

Senior Physical Design Implementation Engineer

Would you like to work for one of the global semiconductor leaders? Now hiring for a Senior Physical Design Implementation Engineer to join the team.

Key experience needed for the Senior Physical Design Implementation Engineer role:

• 4+ years of hands-on experience working in Physical Design.
• Strong grasp of the full PD lifecycle, from netlist handoff through GDS, including floorplanning, power planning, placement, CTS, routing, and associated optimization.
• Solid background using advanced-node physical design tools (10nm and below) for implementation and signoff.
• Deep understanding of STA concepts, timing-closure strategies, and how timing impacts congestion, routing quality, and power.
• Familiarity with power analysis and power-integrity evaluation techniques.
• Working knowledge of Physical Verification flows and achieving DRC-clean layouts.

Keywords: ASIC / Physical Design / SoC / RTL / GDS / Place & Route / STA / RTL-to-GDS / IP Design / Digital Design / Cadence / Synopsys / Semiconductor / Timing Closure / PPA Optimization

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