Digital Design Engineer

European Tech Recruit; Ireland; On-site; EUR 70,000 - 95,000; Full time

Job summary

European Tech Recruit is assisting a leading semiconductor company in Ireland to hire a Digital ASIC Engineer. You will contribute to end-to-end design of digital blocks for consumer devices, work with RTL, SystemVerilog, and Python tooling, and help deliver timing-closed netlists for layout.

You’ll collaborate with systems architects and other HW/SW engineers to integrate blocks into larger chip designs, perform synthesis and timing closure, and support low-power design considerations.

Qualifications

• Degree in engineering or science required.
• Solid RTL design and SystemVerilog experience.
• Proficient in scripting (Python/Tcl/Perl) and 2+ years in Digital TRL design.

Responsibilities

• Design and code digital logic blocks for chip integration.
• Verify designs against test benches and fix bugs.
• Handle synthesis and timing closure with standard EDA tools.
• Consider power budgets and contribute to low-power design decisions.
• Write scripts to speed up team processes.
• Collaborate with systems architects and HW/SW engineers to integrate blocks into larger chip designs.

Skills

RTL Design

SystemVerilog

Python scripting

C++/SystemC

Education

Engineering or science degree

Tools

PrimeTime/PTPX

LEC

Synthesis tools

Job description

Digital ASIC Engineer

Our client, a well-established semiconductor business supplying chip IP into consumer electronics, is looking to add a Digital ASIC Engineer to their design team. The role sits within a group responsible for custom digital blocks that end up inside phones, wearables, connected vehicles and other everyday hardware.

You’ll be involved end-to-end: writing specs, coding and verifying RTL, running synthesis, and handing off clean, timing-closed netlists ready for layout. It’s a genuinely collaborative role, you’ll be working alongside systems architects and other hardware/software engineers to get digital blocks integrated cleanly into larger chip designs.

Day to day, you’ll be:

• Designing and coding digital logic blocks destined for chip integration
• Verifying designs against test benches, chasing down and fixing bugs
• Handling synthesis and timing closure work using standard EDA signoff tools
• Looking at power budgets and helping shape low-power design choices
• Writing scripts/tooling (Python) to speed up team processes
• Working with other engineering functions and supporting release governance

On paper, we’d like to see:

• A relevant engineering or science degree
• Solid RTL Design experinece as well as comfortable in SystemVerilog, plus scripting (Python/Tcl/Perl)
• 2+ years of Digital TRL Design experience in a professional setting
• Solid tooling exposure; synthesis, LEC, PrimeTime/PTPX or similar signoff tools
• Nice to have: ECO experience, DRC/CDC checks, C++/SystemC, DFT/MBIST exposure
• A clear communicator who’s happy working at pace in a team setting

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