Staff Design Engineer: Edge AI Subsystems

ARM; United Kingdom; On-site; GBP 97,000 - 132,000; Full time

Benefits offered by this job

Health and wellness programs

Flexible work arrangements

Financial rewards and benefits beyond薪

Job summary

ARM is seeking a Staff Design Engineer to join the IP and Technology team within the Solutions Engineering department. You will help develop subsystem solutions and SoC IPs for Edge AI, Physical AI, and Cloud AI, collaborating with engineers across teams to deliver high‑quality designs.

The role requires extensive RTL design with SystemVerilog/Verilog, deep microarchitecture knowledge, and familiarity with AMBA AXI/APB interfaces.

Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering or related field.
• 10+ years of relevant industry experience.
• Extensive hands-on RTL design and microarchitecture experience.
• Proven track record delivering IP or RTL subsystems.
• Familiarity with AMBA AXI/APB and industry EDA tools.

Responsibilities

• Analyze architectural and system specs to refine solutions.
• Develop microarchitecture specs for subsystems/IP from high-level requirements.
• Design IP/subsystems and integrate existing Arm IP with third-party IP.
• Ensure robust IP functionality and system-level interfaces.
• Maintain design intent and timing/power constraints (UPF).
• Perform design checks: Lint, CDC, RDC, X-propagation, synthesis.
• Collaborate with verification teams to review tests and debug issues.
• Work with performance, power teams to meet timing, area, power goals.
• Improve design methodologies and project delivery timelines.
• Provide guidance and participate in design reviews.

Skills

Digital RTL design

Microarchitecture development

SystemVerilog/Verilog

AMBA AXI/APB interfaces

Design for low power

Collaboration across teams

Education

Bachelor’s/Master’s/PhD in Electrical/Electronic/Computer Engineering or related

Tools

SystemVerilog

EDA tools

Job description

ARM is seeking a Staff Design Engineer to join the IP and Technology team within the Solutions Engineering department. You will help develop subsystem solutions and SoC IPs for Edge AI, Physical AI, and Cloud AI, collaborating with engineers across teams to deliver high‑quality designs.

The role requires extensive RTL design with SystemVerilog/Verilog, deep microarchitecture knowledge, and familiarity with AMBA AXI/APB interfaces.