Staff RTL Engineer – AI-Driven Hardware & Verification

ARM; Saffron Walden; Híbrido; GBP 65.000 - 100.000; Jornada completa

Descripción de la vacante

ARM LIMITED is seeking an experienced hardware design engineer to turn architectural requirements into efficient digital RTL, balancing performance and power. You will develop synthesizable RTL, build verification environments, and integrate IP blocks while collaborating across engineering teams.

The role emphasises optimization, use of synthesis results for gate-level builds, and exploring AI-assisted tooling to improve hardware design workflows. Hybrid working is available.

Formación

• Experience designing and verifying synthesizable RTL using SystemVerilog or Verilog.
• Ability to develop and maintain testbenches and investigate functional verification issues.
• Experience using synthesis to evaluate RTL implementation results and support gate-level builds.
• Ability to analyse technical problems, communicate design decisions clearly and collaborate across engineering disciplines.

Responsabilidades

• Design, develop and maintain synthesizable RTL using SystemVerilog or Verilog.
• Translate architectural and functional requirements into efficient hardware implementations.
• Develop verification environments, including testbenches, and perform functional verification.
• Integrate digital IP blocks and subsystems, including interfaces, control logic and datapaths.
• Partner with system architects and engineering teams to evaluate performance, power and area trade-offs.
• Debug, optimise and integrate RTL, and use synthesis results to assess implementation outcomes.
• Improve hardware development workflows through automation and exploration of AI-assisted tooling.

Conocimientos

RTL design

Verification

SystemVerilog/Verilog

Analytical problem solving

Herramientas

Synthesis

FPGA

Testbenches

Descripción del empleo

ARM LIMITED is seeking an experienced hardware design engineer to turn architectural requirements into efficient digital RTL, balancing performance and power. You will develop synthesizable RTL, build verification environments, and integrate IP blocks while collaborating across engineering teams.

The role emphasises optimization, use of synthesis results for gate-level builds, and exploring AI-assisted tooling to improve hardware design workflows. Hybrid working is available.