Staff Hardware Engineer: RTL, Verification & Automation

Arm; Cambridge; Híbrido; GBP 97.000 - 132.000; Jornada completa

Descripción de la vacante

Arm in Cambridge is seeking a Staff Hardware Engineer to design, verify and optimise digital hardware across RTL, verification and synthesis. You will translate architecture into efficient implementations and collaborate with architects to balance performance, power, and area.

The role explores AI-assisted tools and automation to improve design and verification workflows, with opportunities to influence hardware development across the lifecycle. Hybrid working is supported.

Formación

• Experience designing and verifying synthesizable RTL using SystemVerilog or Verilog.
• Ability to develop and maintain testbenches and investigate functional verification issues.
• Experience using synthesis to evaluate RTL implementation results and support gate-level builds.
• Ability to analyse technical problems, communicate design decisions clearly and collaborate across engineering disciplines.

Responsabilidades

• Design, develop and maintain synthesizable RTL using SystemVerilog or Verilog.
• Translate architectural and functional requirements into efficient hardware implementations.
• Develop verification environments, including testbenches, and perform functional verification.
• Integrate digital IP blocks and subsystems, including interfaces, control logic and datapaths.
• Partner with system architects and engineering teams to evaluate performance, power and area trade-offs.
• Debug, optimise and integrate RTL, and use synthesis results to assess implementation outcomes.
• Improve hardware development workflows through automation and exploration of AI-assisted tooling.

Conocimientos

RTL design

SystemVerilog

Verilog

Functional verification

Synthesis

Testbenches

AI-assisted tools

Herramientas

FPGA build

Descripción del empleo

Arm in Cambridge is seeking a Staff Hardware Engineer to design, verify and optimise digital hardware across RTL, verification and synthesis. You will translate architecture into efficient implementations and collaborate with architects to balance performance, power, and area.

The role explores AI-assisted tools and automation to improve design and verification workflows, with opportunities to influence hardware development across the lifecycle. Hybrid working is supported.