Senior Verification Engineer – ASIC/FPGA RTL SystemVerilog/UVM

Yoh Solutions Ltd; Greater London; Presencial; GBP 70.000 - 90.000; Jornada completa

Descripción de la vacante

Yoh Solutions Ltd. is seeking a Senior Verification Engineer to join our engineering team in the UK, with work in Bristol or Cambridge.

You will plan, develop and execute verification activities for complex digital designs within an ASIC/FPGA environment, ensuring robust methodologies and high-quality deliverables before production deployment. You will build SystemVerilog/UVM verification environments, testbenches and coverage models, while collaborating across design, FPGA and systems teams.

Formación

• Degree in Electronic/Computer Engineering required.
• Proven experience verifying ASIC/FPGA.
• Strong SystemVerilog and UVM expertise.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting (Python, Tcl, Bash).

Responsabilidades

• Develop and execute verification strategies for complex ASIC and FPGA designs.
• Create and maintain SystemVerilog/UVM testbenches and coverage models.
• Debug RTL and verification issues to meet quality and performance requirements.
• Collaborate with design, FPGA and systems teams throughout the development lifecycle.
• Support automation, regression testing and continuous improvement initiatives.
• Mentor junior engineers and participate in technical reviews.

Conocimientos

SystemVerilog

UVM

RTL design

Linux scripting

Debugging

Communication

Mentoring

Educación

Degree in Electronic Engineering / Computer Engineering

Descripción del empleo

Yoh Solutions Ltd. is seeking a Senior Verification Engineer to join our engineering team in the UK, with work in Bristol or Cambridge.

You will plan, develop and execute verification activities for complex digital designs within an ASIC/FPGA environment, ensuring robust methodologies and high-quality deliverables before production deployment. You will build SystemVerilog/UVM verification environments, testbenches and coverage models, while collaborating across design, FPGA and systems teams.