Senior ASIC Verification Engineer — SystemVerilog/UVM Expert

Empiric; West of England, Cambridge; On-site; GBP 70,000 - 100,000; Full time

Job summary

Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/SystemVerilog testbenches, and own verification plans for SoC/IP blocks.

The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/SystemVerilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to

Qualifications

• Proven expertise in ASIC verification with SystemVerilog/UVM.
• Experience designing and maintaining advanced verification environments.
• Strong debugging, waveform analysis, and regression management skills.

Responsibilities

• Lead ASIC verification across complex digital designs.
• Develop constrained-random stimuli, assertions, and functional coverage.
• Create and maintain high-quality verification plans and testbenches.
• Collaborate with RTL designers to resolve issues and sign-off.
• Optimise verification environments for faster regression cycles.

Skills

SystemVerilog

UVM

Constrained-random stimulus

Functional coverage

RTL verification

SoC/IP verification

HPC knowledge

Collaboration with RTL

Debugging

Education

Bachelor's degree in Electrical/Electronics Engineering

Tools

UVM testbench development

Waveform analysis tools

Job description

Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/SystemVerilog testbenches, and own verification plans for SoC/IP blocks.

The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/SystemVerilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to