Senior Verification Engineer

Yoh Solutions Ltd; Greater London; On-site; GBP 70,000 - 90,000; Full time

Job summary

Yoh Solutions Ltd. is seeking a Senior Verification Engineer to join our engineering team in the UK, with work in Bristol or Cambridge.

You will plan, develop and execute verification activities for complex digital designs within an ASIC/FPGA environment, ensuring robust methodologies and high-quality deliverables before production deployment. You will build SystemVerilog/UVM verification environments, testbenches and coverage models, while collaborating across design, FPGA and systems teams.

Qualifications

• Degree in Electronic/Computer Engineering required.
• Proven experience verifying ASIC/FPGA.
• Strong SystemVerilog and UVM expertise.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting (Python, Tcl, Bash).

Responsibilities

• Develop and execute verification strategies for complex ASIC and FPGA designs.
• Create and maintain SystemVerilog/UVM testbenches and coverage models.
• Debug RTL and verification issues to meet quality and performance requirements.
• Collaborate with design, FPGA and systems teams throughout the development lifecycle.
• Support automation, regression testing and continuous improvement initiatives.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog

UVM

RTL design

Linux scripting

Debugging

Communication

Mentoring

Education

Degree in Electronic Engineering / Computer Engineering

Job description

Where?: Bristol or Cambridge

What?: Permanent or Contract

An innovative technology company developing advanced digital hardware and signal processing solutions is seeking a Senior Verification Engineer to join its growing engineering team in either

Working within a collaborative ASIC and FPGA development environment, you will play a key role in verifying complex RTL designs, ensuring products meet functional, quality and performance requirements before deployment into production hardware.

This is an excellent opportunity to work on technically challenging projects alongside experienced hardware, FPGA and verification engineers.

The Role

As a Senior Verification Engineer, you will be responsible for planning, developing and executing verification activities for complex digital designs and subsystems.

You will work closely with design engineers throughout the development lifecycle, helping to ensure robust verification methodologies, high-quality deliverables and successful project outcomes.

Key Responsibilities

• Develop and execute verification strategies for complex ASIC and FPGA designs.
• Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models.
• Debug RTL and verification issues, ensuring designs meet quality and performance requirements.
• Collaborate with design, FPGA and systems teams throughout the development lifecycle.
• Support automation, regression testing and continuous improvement initiatives.
• Mentor junior engineers and contribute to technical reviews.

Essential Skills & Experience

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• Proven experience verifying ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Good understanding of RTL design and digital hardware development.
• Experience with coverage-driven and assertion-based verification techniques.
• Linux proficiency and scripting skills (Python, Tcl, Bash or similar).
• Strong debugging, analytical and communication skills.

Desirable Experience

• Communications, networking, aerospace, defence or other high-performance digital systems.
• Digital signal processing (DSP) or complex hardware architectures.
• Formal Verification or FPGA prototyping.
• CI/CD, automated regression environments or MATLAB/Simulink.