Senior SoC Verification Engineer — UVM & SystemVerilog

Infoplus Technologies UK Limited; Cambridge; Hybrid; GBP 96,000 - 125,000; Full time

Job summary

Infoplus Technologies UK Limited is seeking experienced SoC Design Verification (DV) Engineers to verify a next-generation multi-die SoC using SystemVerilog/UVM. Strong debugging skills and C-based test development are essential as embedded cores are used for processor-driven verification.

Role involves subsystem- and SoC-level verification, regression execution, and collaboration with verification planning.

Qualifications

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience modifying, extending, and debugging existing UVM testbenches.
• Knowledge of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem or SoC level functional verification.
• Understanding SoC architectures, bus protocols, and processor peripherals.
• Experience developing, executing, or debugging embedded C tests for SoC verification.
• Ability to debug RTL simulation failures with standard simulators and waveform tools.
• Experience executing regressions and driving coverage closure.
• Proficiency in Python, Perl, or shell scripting.
• Familiarity with version control and verification development workflows.

Responsibilities

• Subystem and SoC functional verification.
• Reuse and enhancement of System Verilog/UVM testbenches.
• Develop and verify processor-based C tests for SoC verification.
• Run regressions, debug failures, and drive coverage closure.
• Collaborate on verification planning and cross-team reviews.

Skills

System Verilog

UVM

SoC verification

C programming

Debugging

Functional coverage

Gate-level simulation

Python scripting

Shell scripting

Education

Electronics/EE/VLSI degree

Tools

Verilog simulators

Waveform tools

Job description

Infoplus Technologies UK Limited is seeking experienced SoC Design Verification (DV) Engineers to verify a next-generation multi-die SoC using SystemVerilog/UVM. Strong debugging skills and C-based test development are essential as embedded cores are used for processor-driven verification.

Role involves subsystem- and SoC-level verification, regression execution, and collaboration with verification planning.