Design Verification Engineer

IT WORLD LIMITED; Cambridge; Presencial; GBP 60.000 - 90.000; Jornada completa

Descripción de la vacante

IT WORLD LIMITED is seeking experienced SoC Design Verification (DV) Engineers to verify a next-generation multi-die SoC for Cambridge with some Bristol work. You will perform subsystem- and SoC-level verification using SystemVerilog/UVM, and develop embedded C tests for processor-driven verification.

The role emphasizes debugging, RTL and SoC architecture understanding, and adapting existing verification environments to evolving designs. Strong scripting skills are valued.

Formación

• Strong hands-on experience with digital design verification using SystemVerilog and UVM.
• Experience modifying and debugging existing UVM testbenches and reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level verification.
• Embedded C test development and verification for processor-based SoC verification.

Responsabilidades

• Subsystem and SoC functional verification.
• Reuse and enhancement of SystemVerilog/UVM testbenches.
• Develop and verify processor-based C tests for SoC verification.
• Execute regressions, debug failures, and drive coverage closure.
• Support verification planning and cross-team collaboration.

Conocimientos

SystemVerilog

UVM

Embedded C

Regression testing

RTL debugging

Python scripting

Educación

Bachelor's or Master's in Electronics or related

Herramientas

waveform simulators

Descripción del empleo

Work Location – Cambridge and Bristol, UK(min 3 days in a week from client)

Role Overview

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.

Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on embedded processor cores.

The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities-

1. 1. Subsystem and SoC Functional Verification
2. 2. System Verilog/UVM Testbench Reuse and Enhancement
3. 3. Processor-Based C Test Development and Verification
4. 4. Regression Execution, Debugging, and Coverage Closure
5. 5. Verification Planning and Collaboration

Required Technical Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analyzing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows.

Candidate Profile

The ideal candidate should:

• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.
• Demonstrate the ability to analyze design changes and identify required verification updates.
• Possess strong RTL debugging and problem-solving capabilities.
• Have experience working with large SoC verification regressions.
• Be capable of independently owning verification activities for assigned subsystems.
• Understand the relationship between UVM-based verification and processor-driven C test verification.

Educational Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.