SoC Design Verification Engineer

W3Global; Cambridge; Presencial; GBP 70.000 - 90.000; Jornada completa

Descripción de la vacante

W3Global is seeking an experienced SoC Design Verification Engineer to join their Cambridge/Bristol team on a 6-month contract. The role focuses on functional verification of next-generation multi-die SoCs using SystemVerilog/UVM, with processor-driven verification in C on embedded cores.

Strong debugging, analytical skills and ARM-based SoC understanding are required. You will work on subsystem- and SoC-level verification, reuse/extend existing testbenches, and drive coverage closure and

Formación

• Experience in digital design verification using SystemVerilog and UVM.
• Ability to modify and extend existing UVM testbenches.
• Understanding of constrained-random verification and functional coverage.
• Experience in subsystem-level or SoC-level verification.
• Strong RTL debugging and problem solving.

Responsabilidades

• Perform subsystem and SoC functional verification.
• Reuse and enhance SystemVerilog/UVM testbenches.
• Develop and verify processor-based C tests for SoC verification.
• Run regressions, debug failures, and close coverage gaps.
• Coordinate verification plans with design and validation teams.

Conocimientos

SystemVerilog

UVM

SoC Verification

C

Debugging

Functional Coverage

Gate level simulation

Python / scripting

Regression management

Educación

Bachelor's or Master's in Electronics / Electrical / Computer Engineering / VLSI

Descripción del empleo

Job Role : SoC Design Verification Engineer

Work Location - Cambridge and Bristol, UK

Mode of Hiring- 6 Months Contract Position

Experience Level- min 5+ to 20 years

Demand is firm, pls. enable supply asap.

Job Description - SoC Design Verification Engineer

Position:

Design Verification Engineer / Senior Design Verification Engineer

Domain:

Semiconductor - Multi-Chip System-on-Chip (SoC)

Experience:

5 to 20 years

Key Skills:

System Verilog, UVM, SoC Verification, C, Debugging, Functional Coverage, Gate level simulation

Role Overview

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design. Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on embedded processor cores. The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities

• Subsystem and SoC Functional Verification
• System Verilog/UVM Testbench Reuse and Enhancement
• Processor-Based C Test Development and Verification
• Regression Execution, Debugging, and Coverage Closure
• Verification Planning and Collaboration

Required Technical Skills

Essential Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analyzing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows.

Candidate Profile

The Ideal Candidate Should

• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.
• Demonstrate the ability to analyze design changes and identify required verification updates.
• Possess strong RTL debugging and problem-solving capabilities.
• Have experience working with large SoC verification regressions.
• Be capable of independently owning verification activities for assigned subsystems.
• Understand the relationship between UVM-based verification and processor-driven C test verification.

Educational Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.

Key Hiring Priorities

Candidates Will Be Evaluated Primarily On

• System Verilog/UVM proficiency - Ability to understand, modify, and debug existing verification environments.
• SoC/subsystem verification experience - Practical experience with complex RTL designs and subsystem interactions.
• Debugging and problem-solving skills - Ability to independently investigate simulation failures and identify root causes.
• Processor-based C verification - Experience developing or debugging C tests running on SoC processor cores.
• Verification reuse and regression management - Ability to efficiently adapt existing testbenches and test suites to design changes.
• Coverage and verification closure - Experience identifying verification gaps and achieving sign-off objectives.