SoC Design Verification Engineer

Infoplus Technologies UK Limited; Cambridge; Híbrido; GBP 96.000 - 125.000; Jornada completa

Descripción de la vacante

Infoplus Technologies UK Limited is seeking experienced SoC Design Verification (DV) Engineers to verify a next-generation multi-die SoC using SystemVerilog/UVM. Strong debugging skills and C-based test development are essential as embedded cores are used for processor-driven verification.

Role involves subsystem- and SoC-level verification, regression execution, and collaboration with verification planning.

Formación

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience modifying, extending, and debugging existing UVM testbenches.
• Knowledge of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem or SoC level functional verification.
• Understanding SoC architectures, bus protocols, and processor peripherals.
• Experience developing, executing, or debugging embedded C tests for SoC verification.
• Ability to debug RTL simulation failures with standard simulators and waveform tools.
• Experience executing regressions and driving coverage closure.
• Proficiency in Python, Perl, or shell scripting.
• Familiarity with version control and verification development workflows.

Responsabilidades

• Subystem and SoC functional verification.
• Reuse and enhancement of System Verilog/UVM testbenches.
• Develop and verify processor-based C tests for SoC verification.
• Run regressions, debug failures, and drive coverage closure.
• Collaborate on verification planning and cross-team reviews.

Conocimientos

System Verilog

UVM

SoC verification

C programming

Debugging

Functional coverage

Gate-level simulation

Python scripting

Shell scripting

Educación

Electronics/EE/VLSI degree

Herramientas

Verilog simulators

Waveform tools

Descripción del empleo

• Work Location: Cambridge and Bristol, UK (Candidate can report to either location)
• Domain: Semiconductor - Multi-Chip System-on-Chip (SoC)
• Mode of Hiring: 6-month contract position with the possibility of extension
• Work location: 03 Days/week at the client's office
• Experience: 7+ Years
• Key Skills: System Verilog, UVM, SoC Verification, C, Debugging, Functional Coverage, Gate-level simulation

Role Overview

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.

Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on embedded processor cores.

The role requires strong debugging and analytical skills, an understanding of ARM processor-based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities-

• 1. Subsystem and SoC Functional Verification
• 2. System Verilog/UVM Testbench Reuse and Enhancement
• 3. Processor-Based C Test Development and Verification
• 4. Regression Execution, Debugging, and Coverage Closure
• 5. Verification Planning and Collaboration

Required Technical Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analysing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows.

Candidate Profile

The ideal candidate should:

• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.
• Demonstrate the ability to analyse design changes and identify required verification updates.
• Possess strong RTL debugging and problem-solving capabilities.
• Have experience working with large SoC verification regressions.
• Be capable of independently owning verification activities for assigned subsystems.
• Understand the relationship between UVM-based verification and processor-driven C test verification.

Educational Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.

Key Hiring Priorities

Candidates will be evaluated primarily on:

• System Verilog/UVM proficiency – Ability to understand, modify, and debug existing verification environments.
• SoC/subsystem verification experience – Practical experience with complex RTL designs and subsystem interactions.
• Debugging and problem-solving skills – Ability to independently investigate simulation failures and identify root causes.
• Processor-based C verification – Experience developing or debugging C tests running on SoC processor cores.
• Verification reuse and regression management – Ability to efficiently adapt existing testbenches and test suites to design changes.
• Coverage and verification closure – Experience identifying verification gaps and achieving sign-off objectives.