SoC DV Engineer: SystemVerilog/UVM & Embedded C Verification

SmartEdge, Lda; West of England; On-site; GBP 65,000 - 90,000; Full time

Job summary

SmartEdge, Lda is seeking experienced SoC Design Verification Engineers to verify a next-generation multi-die SoC. You will perform subsystem and SoC-level verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.

Ideal candidates have strong debugging skills, understand ARM-based SoC architectures, and can adapt existing verification environments to evolving design requirements while contributing to regression planning and coverage closure.

Qualifications

• Experience in digital design verification using System Verilog and UVM.
• Experience modifying, extending, and debugging existing UVM testbenches.
• Understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level verification.
• Strong understanding of SoC architectures, bus protocols, and processor peripherals.
• Experience developing, executing, or debugging embedded C tests for SoC verification.
• Ability to debug RTL simulation failures using industry-standard simulators and waveform tools.
• Experience executing regressions, analyzing failures, and driving coverage closure.
• Proficiency with scripting (Python/Perl/shell) and version control workflows.

Responsibilities

• Subsystem and SoC functional verification.
• SystemVerilog/UVM testbench reuse and enhancement.
• Processor-based C test development and verification.
• Regression execution, debugging, and coverage closure.
• Verification planning and collaboration.

Skills

System Verilog

UVM

Constrained-random verification

Functional coverage

Assertions & checkers

C tests for processor verification

Python/Perl/shell scripting

Version control

RTL debugging

Education

Bachelor's or Master's degree in Electronics / Electrical Engineering / Computer Engineering / VLSI

Tools

RTL simulators

Waveform debugging tools

Job description

SmartEdge, Lda is seeking experienced SoC Design Verification Engineers to verify a next-generation multi-die SoC. You will perform subsystem and SoC-level verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.

Ideal candidates have strong debugging skills, understand ARM-based SoC architectures, and can adapt existing verification environments to evolving design requirements while contributing to regression planning and coverage closure.