SoC Verification Engineer – UVM/C Tests (Contract)

Intuition IT Solutions; Cambridge; On-site; GBP 65,000 - 90,000; Full time

Job summary

Intuition IT Solutions is seeking experienced SoC Design Verification (DV) Engineers to verify next-generation multi-die SoC designs in a contract role (Inside IR35). The work involves subsystem and SoC-level verification using SystemVerilog/UVM and processor-driven C tests on embedded cores.

Candidates should have hands-on SV/UVM verification, experience with existing UVM testbenches, and a strong grasp of SoC architectures and bus protocols.

Qualifications

• Experience with SystemVerilog/UVM-based verification environments.
• Familiarity with constrained-random verification, coverage, assertions, scoreboards, and checkers.
• Ability to debug and enhance existing UVM testbenches and verification components.
• Experience in subsystem- or SoC-level verification.
• Understanding of ARM-based SoC architectures and peripherals.

Responsibilities

• Subsystem- and SoC-level functional verification.
• Reuse and enhancement of SystemVerilog/UVM testbenches.
• Development and verification of processor-based C tests.
• Run regressions, debug failures, and drive coverage closure.
• Collaborate on verification planning and execution.

Skills

SystemVerilog

UVM

Embedded C

Python scripting

SoC architecture

Debugging RTL

Bus protocols

Education

Bachelor's or Master’s in Electronics/EE/CE/VLSI

Tools

Verilog simulators

Waveform tools

Version control

Job description

Intuition IT Solutions is seeking experienced SoC Design Verification (DV) Engineers to verify next-generation multi-die SoC designs in a contract role (Inside IR35). The work involves subsystem and SoC-level verification using SystemVerilog/UVM and processor-driven C tests on embedded cores.

Candidates should have hands-on SV/UVM verification, experience with existing UVM testbenches, and a strong grasp of SoC architectures and bus protocols.