Senior CPU RTL Engineer (RISC‑V, Chisel)

SiFive, Inc.; United Kingdom; On-site; GBP 60,000 - 80,000; Full time

Job summary

A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators. The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.

Qualifications

• 3+ years of design experience.
• Academic or professional experience with CPU RTL design.
• Ability to collaborate in a dynamic team environment.

Responsibilities

• Architect, design and implement features in RISC-V CPU core generators.
• Integrate design content into Chisel/FIRRTL framework.
• Collaborate with design verification team for test plans.

Skills

Verilog/System Verilog/VHDL

Object-oriented programming

Functional programming

Test-driven development

Attention to detail

Education

BS/MS in Computer Science, Computer Engineering, Electrical Engineering

Tools

Git/Github

Jira

Confluence

Job description

A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators. The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.