Senior RTL CPU Engineer - Next-Gen Processor IP

IC Resources; Cambridge; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Annual bonus

Equity/stock options

Comprehensive benefits

Job summary

IC Resources is seeking a Senior RTL Design Engineer to join a global semiconductor leader driving next‑generation CPU technology. You will work on designing CPU cores, across the full design lifecycle, collaborating with world‑class architects and engineers on ambitious, technically demanding projects.

The role requires 3+ years in RTL design, strong Verilog/SystemVerilog/VHDL skills, and a solid software background (C, C++, Python) with DSLs and adaptive unit tests.

Qualifications

• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related discipline (or equivalent industry experience)
• 3+ years’ experience in RTL design
• Academic or commercial experience in CPU RTL design
• Strong RTL design skills using Verilog, SystemVerilog, or VHDL
• A solid software engineering background, including experience with: Object‑oriented and functional programming paradigms – C, C++, Python; Compiler infrastructures, particularly DSLs; Test‑driven development and writing adaptive unit tests

Responsibilities

• Design industry‑leading CPU cores across the full design lifecycle
• Collaborate with architects and design engineers on technically demanding projects
• Contribute to cutting‑edge processor development and verify robust designs

Skills

RTL design

Verilog

SystemVerilog

VHDL

C

C++

Python

DSLs

Unit tests

UVM

Education

Bachelors or Masters in CS/CE/EE

Tools

Compiler infrastructures

Job description

IC Resources is seeking a Senior RTL Design Engineer to join a global semiconductor leader driving next‑generation CPU technology. You will work on designing CPU cores, across the full design lifecycle, collaborating with world‑class architects and engineers on ambitious, technically demanding projects.

The role requires 3+ years in RTL design, strong Verilog/SystemVerilog/VHDL skills, and a solid software background (C, C++, Python) with DSLs and adaptive unit tests.