RISC-V Interconnect Architect: Configurable RTL Generators

SiFive; Cambridge; On-site; GBP 117,809 - 143,989; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

A leading technology company in Cambridge is seeking a passionate staff level hardware engineer to design industry-leading CPU and interconnect IP. Responsibilities include architecting enhanced TileLink interconnects and implementing RTL generators. Candidates should have a strong software engineering background and proficiency in Verilog, SystemVerilog, or VHDL. This opportunity offers a competitive salary range of $158,760.00 – $194,040.00, comprehensive benefits, and a commitment to an inclusive work environment.

Qualifications

• Experience with NoC or other interconnect fabrics.
• Familiarity with industry-standard bus protocols.
• Ability to architect solutions for connecting disparate bus fabrics.

Responsibilities

• Architect, design, and implement an enhanced TileLink interconnect.
• Integrate new design content and contribute to improvements.
• Ensure knowledge sharing through documentation.

Skills

Knowledge of cache and cache coherency architectures and concepts

Software engineering skills

Proficiency with hardware design in Verilog, SystemVerilog, or VHDL

Attention to detail and high-quality design focus

Ability to work well with others

Education

BS/MS in EE, CE, CS or related technical discipline

Tools

Git

GitHub

Jira

Confluence

Job description

A leading technology company in Cambridge is seeking a passionate staff level hardware engineer to design industry-leading CPU and interconnect IP. Responsibilities include architecting enhanced TileLink interconnects and implementing RTL generators. Candidates should have a strong software engineering background and proficiency in Verilog, SystemVerilog, or VHDL. This opportunity offers a competitive salary range of $158,760.00 – $194,040.00, comprehensive benefits, and a commitment to an inclusive work environment.