Senior Analog/Mixed-Signal Design & Modelling Engineer – Cryo-CMOS

Ionq; Oxford; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

IonQ in Oxford is seeking a Senior Staff Analog Mixed-Signal Design and Modelling Engineer to join the Cryo-CMOS IC team. You will design analog and mixed-signal blocks from specification through tape-out and silicon validation, owning the full-chip model and its integration.

The role demands deep expertise in Verilog-A/Verilog-AMS and SystemVerilog real-number modelling, plus experience with Cadence AMS Designer and Xcelium.

Qualifications

• Deep analog and mixed-signal design and modelling experience, typically 10+ years.
• Experience designing blocks proven in silicon and models used in production tape-out flows.
• Expert transistor-level design of precision analog blocks through PVT and Monte Carlo, layout and silicon validation.
• Fluency with production Cadence flow and scripting for model generation and regression.

Responsibilities

• Own full-chip modelling strategy: model architecture, abstraction levels, accuracy targets and sign-off criteria used across the IC development flow
• Owning analog and mixed-signal blocks (references, DACs, switches, regulators, clock distribution) from specification through schematic design
• Own top-level integration: define block interfaces and specifications, assemble the top level, and run the full-chip mixed-signal simulations that verify the ASIC
• Develop Verilog-A and Verilog-AMS models of analog blocks and assemble them into a simulatable full chip
• Build real-number models so the full chip runs in digital verification and regression at practical speed
• Derive models from mathematics: turn a transfer function, a Z-parameter network description or a MATLAB analysis into robust Verilog-A with well-behaved tolerances
• Lead block-level design reviews and mentor engineers on circuit design and modelling craft

Skills

Analog design

Mixed-signal design

Verilog-A / Verilog-AMS

SystemVerilog

Mathematical modelling

Cadence AMS Designer

Xcelium

Tools

Cadence AMS Designer

Xcelium

Verilog-A

Verilog-AMS

MATLAB

Python

Job description

IonQ in Oxford is seeking a Senior Staff Analog Mixed-Signal Design and Modelling Engineer to join the Cryo-CMOS IC team. You will design analog and mixed-signal blocks from specification through tape-out and silicon validation, owning the full-chip model and its integration.

The role demands deep expertise in Verilog-A/Verilog-AMS and SystemVerilog real-number modelling, plus experience with Cadence AMS Designer and Xcelium.