Senior Analog Mixed-Signal Design & Modelling Engineer

NightDragon Acquisition Corp.; Oxford; Hybrid; GBP 90,000 - 140,000; Full time

Benefits offered by this job

Comprehensive medical/dental/vision

401(k)

Unlimited PTO & holidays

Parental/adoption leave

Home technology stipend

Job summary

IonQ in Oxford seeks a Staff Analog Mixed-Signal Design and Modelling Engineer to lead AMS modelling for ASICs used in trapped-ion quantum processors. You will develop behavioural models, verify block and full-chip behaviour, and mentor a team of engineers in model accuracy and regression performance.

You will collaborate with analog designers and system teams, drive tape-out readiness, and shape sign-off criteria to ensure reliable control electronics for quantum computing systems.

Qualifications

• Deep analog and mixed-signal design and modelling experience (10+ years).
• Proven transistor-level design of precision analog blocks with PVT and Monte‑Carlo.
• Expert Verilog-A/Verilog‑AMS modelling and strong regression methodology.
• Fluency with MATLAB or Python for analysis and model validation.
• Production tape-out flows experience and silicon bring-up.

Responsibilities

• Lead full-chip modelling strategy across IC development flow.
• Develop Verilog-A/Verilog-AMS models and assemble into a simulatable full chip.
• Define interfaces, run mixed-signal simulations, and verify against silicon.
• Mentor engineers and lead design reviews and sign-off criteria.
• Drive model-versus-schematic correlation using measured silicon data.

Skills

Analog/mixed-signal design

Verilog-A/Verilog-AMS

SystemVerilog

Matlab/Python

Cadence AMS Designer

Xcelium/Spectre

Silicon bring-up

Tape-out

Mentoring

Tools

Cadence AMS Designer

Xcelium

Spectre

Verilog-A

Verilog-AMS

MATLAB

Python

Job description

IonQ in Oxford seeks a Staff Analog Mixed-Signal Design and Modelling Engineer to lead AMS modelling for ASICs used in trapped-ion quantum processors. You will develop behavioural models, verify block and full-chip behaviour, and mentor a team of engineers in model accuracy and regression performance.

You will collaborate with analog designers and system teams, drive tape-out readiness, and shape sign-off criteria to ensure reliable control electronics for quantum computing systems.