Senior Silicon Validation Engineer, Cryo-CMOS ASICs(Hybrid)

Capella Space; Oxford; Hybride; GBP 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Stock options

Annual performance bonus

Private medical and dental insurance

Résumé du poste

IonQ Oxford is seeking a Senior Silicon Validation Engineer to lead the validation of analogue and mixed-signal ASICs for trapped-ion quantum processors. You will drive test plans, build platforms, and oversee first-silicon bring-up from room temperature to cryogenic operation.

You will shape validation architecture, develop hardware/software tools, and ensure robust, repeatable results across multiple ASIC generations with tight collaboration across design, verification, and systems teams.

Qualifications

• Substantial experience in analogue or mixed-signal silicon validation and characterisation.
• Ownership of multiple silicon bring-up programmes.
• Hands-on laboratory skills with testability and measurement confidence.

Responsabilités

• Own validation delivery across chip and system interfaces.
• Lead first-silicon bring-up and characterisation of analog and mixed-signal blocks.
• Develop validation boards, fixtures and reusable automation.
• Plan cryogenic measurements and drive root-cause analysis.
• Influence testability before tape-out and coordinate with partners.

Connaissances

Analogue validation

Mixed-signal validation

Python programming

Oscilloscopes and test equipment

Digital/FPGA interfaces

Measurement uncertainty

Formation

Electrical or Electronic Engineering degree

Outils

Python automation

Lab equipment control

Description du poste

IonQ Oxford is seeking a Senior Silicon Validation Engineer to lead the validation of analogue and mixed-signal ASICs for trapped-ion quantum processors. You will drive test plans, build platforms, and oversee first-silicon bring-up from room temperature to cryogenic operation.

You will shape validation architecture, develop hardware/software tools, and ensure robust, repeatable results across multiple ASIC generations with tight collaboration across design, verification, and systems teams.