Senior Analog Mixed-Signal Modelling Engineer (Cryo-CMOS)

IonQ, Inc.; Oxford; Hybrid; GBP 90,000 - 125,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision plans

401(k) matching

Unlimited PTO

Parental/adoption leave

Home technology stipend

Job summary

IonQ Oxford is seeking a Staff Analog Mixed-Signal Design and Modelling Engineer to join the Cryo-CMOS IC team. You will develop behavioural models and mixed-signal verification environments for ASICs used in our trapped-ion quantum processors.

You will lead modelling and verification activities, build full-chip models, and mentor engineers while delivering sign-off criteria and clocking, references, DACs and regulators documentation in a fast-moving, highly technical environment.

Qualifications

• Deep analog and mixed-signal design and modelling experience (10+ years)
• Proven blocks designed in silicon and usable in production tape-out flows
• Expert Verilog-A and Verilog-AMS modelling; strong real-number modelling

Responsibilities

• Own the full-chip modelling strategy: architecture, abstraction levels, accuracy targets and sign-off criteria.
• Own analog and mixed-signal blocks from specification through schematic design.
• Own top-level integration: define interfaces, assemble the top level and run full-chip simulations.
• Build real-number models so the full chip runs in digital verification and regression.
• Derive models from mathematics: transfer functions, Z-parameters, MATLAB analysis to robust Verilog-A.
• Define model-versus-schematic correlation and feed back measured silicon behaviour.
• Develop verification plans covering operating modes, interfaces, and PVT conditions.
• Stand up mixed-signal co-simulation and regression; lead reviews and mentor engineers.
• Lead modelling and verification reviews, define sign-off criteria with the IC Lead, and present coverage and risks.

Skills

Analog/mixed-signal design

Verilog-A

Verilog-AMS

SystemVerilog

MATLAB

Python

Tools

Cadence AMS Designer

Xcelium

Spectre

Verilog-A

Verilog-AMS

Job description

IonQ Oxford is seeking a Staff Analog Mixed-Signal Design and Modelling Engineer to join the Cryo-CMOS IC team. You will develop behavioural models and mixed-signal verification environments for ASICs used in our trapped-ion quantum processors.

You will lead modelling and verification activities, build full-chip models, and mentor engineers while delivering sign-off criteria and clocking, references, DACs and regulators documentation in a fast-moving, highly technical environment.