Senior AMS Design Verification Engineer - Mixed-Signal

Apple, Inc.; Greater London; On-site; GBP 70,000 - 110,000; Full time

Job summary

Apple, Inc. in London seeks an Experienced AMS Design Verification Engineer to enable bug-free first silicon for mixed-signal designs. You will craft verification environments, write test scenarios and assertions, and collaborate with Analog and Digital Design engineers across the AMS DV team.

The role focuses on self-checking verification, SystemVerilog UVM, and power/ timing analyses, with opportunities to advance verification techniques and toolchains in a cutting-edge environment.

Qualifications

• Knowledge of SystemVerilog test-bench language and UVM.
• Hands-on experience with constrained random verification environments.
• Basic design background to support verification results analysis.
• Knowledge of Object Oriented Programming (OOP).
• Proficiency in English language is required.

Responsibilities

• Define and design self-checking verification environments for multi-layer systems.
• Develop verification strategies and execute verification tasks to enable bug-free tape-outs.
• Collaborate with analog and digital design engineers across phases of pre-silicon verification.

Skills

SystemVerilog

UVM (Universal Verification Methodolgy

Constrained random verification

Object Oriented Programming

English language

C++

Python

Verilog

Education

Master’s degree or PhD in Electrical/Computer Engineering or equivalent

Tools

FPGA emulation platforms

Job description

Apple, Inc. in London seeks an Experienced AMS Design Verification Engineer to enable bug-free first silicon for mixed-signal designs. You will craft verification environments, write test scenarios and assertions, and collaborate with Analog and Digital Design engineers across the AMS DV team.

The role focuses on self-checking verification, SystemVerilog UVM, and power/ timing analyses, with opportunities to advance verification techniques and toolchains in a cutting-edge environment.