Design Verification Engineer - Power Management (Early Career or Experienced)

Apple Inc.; Swindon; On-site; GBP 60,000 - 90,000; Full time

Job summary

Apple Inc. is seeking a Design Verification Engineer in Swindon to enable bug-free silicon for mixed-signal designs.

You will craft verification plans, build test benches, and develop automated flows with SystemVerilog, UVM, and other verification tools across RTL and chip-level stages. The role requires strong knowledge of SystemVerilog/UVM, test bench development, and experience in coverage-driven verification.

Qualifications

• Strong knowledge of SystemVerilog and UVM.
• Experience with constrained random verification environments.
• Fluency in English required.

Responsibilities

• Develop verification plans with design leads and architects.
• Build and maintain verification test benches and environments.
• Create directed and constrained random tests and analyze coverage.

Skills

SystemVerilog

UVM

Python

TCL

Education

MS/BS in Computer Science or Electrical Engineering

Tools

VHDL/Verilog

Job description

Summary

At Apple, we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role you will develop verification plans in coordination with design leads and architects. You’ll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.

Minimum Qualifications

Strong knowledge of SystemVerilog and UVMExperience developing scalable and portable test-benchesExperience with constrained random verification environmentsMS/BS in Computer Science or Electrical Engineering or equivalentFluency in English language is required

Preferred Qualifications

Experience defining coverage space, writing coverage model, analyzing resultsExperience with Assertion Based VerificationKnowledge of Object Oriented ProgrammingExperience in Formal Verification (Formal Linting, Formal connectivity, user property verification)Experience with Python, Perl or TCLExcellent communication and interpersonal skills combined with the ability to collaborateBasic knowledge of mixed signal verification