Power Management DV Engineer - Early to Experienced

Apple Inc.; Swindon; On-site; GBP 60,000 - 90,000; Full time

Job summary

Apple Inc. is seeking a Design Verification Engineer in Swindon to enable bug-free silicon for mixed-signal designs.

You will craft verification plans, build test benches, and develop automated flows with SystemVerilog, UVM, and other verification tools across RTL and chip-level stages. The role requires strong knowledge of SystemVerilog/UVM, test bench development, and experience in coverage-driven verification.

Qualifications

• Strong knowledge of SystemVerilog and UVM.
• Experience with constrained random verification environments.
• Fluency in English required.

Responsibilities

• Develop verification plans with design leads and architects.
• Build and maintain verification test benches and environments.
• Create directed and constrained random tests and analyze coverage.

Skills

SystemVerilog

UVM

Python

TCL

Education

MS/BS in Computer Science or Electrical Engineering

Tools

VHDL/Verilog

Job description

Apple Inc. is seeking a Design Verification Engineer in Swindon to enable bug-free silicon for mixed-signal designs.

You will craft verification plans, build test benches, and develop automated flows with SystemVerilog, UVM, and other verification tools across RTL and chip-level stages. The role requires strong knowledge of SystemVerilog/UVM, test bench development, and experience in coverage-driven verification.