Power Management Design Verification Engineer (Early/Experienced)

Lex; Swindon; On-site; GBP 60,000 - 95,000; Full time

Job summary

Apple in Swindon is seeking a driven Design Verification Engineer to enable bug-free silicon for mixed-signal designs. You will develop verification plans, build test benches, and collaborate with Digital and Analog teams to ensure robust pre-silicon validation.

The role requires strong SystemVerilog and UVM skills, experience with constrained random environments, and a degree in CS or EE. Excellent communication and teamwork are essential to help Apple deliver high-quality products to customers

Qualifications

• Strong knowledge of SystemVerilog and UVM.
• Experience developing scalable test-benches.
• Experience with constrained random verification environments.
• MS/BS in Computer Science or Electrical Engineering or equivalent.
• Fluency in English is required.

Responsibilities

• Develop verification plans in coordination with design leads.
• Build and maintain verification test benches and environments.
• Generate directed and constrained random tests.
• Run simulations, debug design and environment issues.
• Sign-off for RTL freeze and tape-out.

Skills

SystemVerilog

UVM

Constrained random

Test benches

RTL verification

English fluency

Education

MS/BS in Computer Science or Electrical Engineering

Tools

VHDL

Verilog

Job description

Apple in Swindon is seeking a driven Design Verification Engineer to enable bug-free silicon for mixed-signal designs. You will develop verification plans, build test benches, and collaborate with Digital and Analog teams to ensure robust pre-silicon validation.

The role requires strong SystemVerilog and UVM skills, experience with constrained random environments, and a degree in CS or EE. Excellent communication and teamwork are essential to help Apple deliver high-quality products to customers