Senior AMS DV Engineer — Mixed-Signal Verification

Apple

Greater London

On-site

GBP 90,000 - 120,000

Full time

46 hours ago
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Job summary

Apple located in London is seeking a forward-thinking Design Verification Engineer to enable bug-free first silicon for mixed-signal designs. You will define verification environments, write test scenarios and assertions, and collaborate closely with Analog and Digital Design engineers to deliver robust validation.

The role emphasizes SystemVerilog/UVM-based verification, constrained random testing, and lab bring-up in a cutting-edge AMS DV team focused on innovative verification techniques.

Qualifications

  • Knowledge of System Verilog test-bench language and UVM.
  • Hands-on experience with constrained random verification environments.
  • Basic design background in support of verification results analysis.
  • Knowledge of Object Oriented Programming (OOP).
  • Proficiency in English language is required.

Responsibilities

  • Design verification environments for multi-layer systems using SystemVerilog UVM.
  • Develop test scenarios and assertions for pre-silicon verification.
  • Collaborate with Analog and Digital Design engineers to enable bug-free tape-outs.
  • Perform power-related analysis and early power estimation scenarios.
  • Support lab bring-up and deliver verification tests for design and test teams.

Skills

SystemVerilog
UVM
OOP
English proficiency
Testbench development

Education

Master's degree or PhD in Electrical/Computer Engineering

Tools

C++
Python
Verilog
FPGA emulation

Job description

Apple located in London is seeking a forward-thinking Design Verification Engineer to enable bug-free first silicon for mixed-signal designs. You will define verification environments, write test scenarios and assertions, and collaborate closely with Analog and Digital Design engineers to deliver robust validation.

The role emphasizes SystemVerilog/UVM-based verification, constrained random testing, and lab bring-up in a cutting-edge AMS DV team focused on innovative verification techniques.

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