Senior AMS DV Engineer — Next-Gen Mixed-Signal Silicon

Apple Inc.; Greater London; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading technology company in Greater London seeks an experienced Design Verification Engineer to join their innovative AMS team. This role entails constructing verification environments, collaborating closely with design engineers, and ensuring high-quality, bug-free designs. Candidates should have a strong background in SystemVerilog and UVM, along with proficiency in Object Oriented Programming. This position offers the chance to work on cutting-edge technologies that impact millions of customers daily.

Qualifications

• Knowledge of System Verilog test‑bench language and UVM.
• Hands-on experience with constrained random verification environments.
• Proficiency in English language is required.

Responsibilities

• Construction of verification environments for mixed-signal designs.
• Coding of test scenarios and assertions.
• Collaboration with Analog and Digital design engineers.

Skills

SystemVerilog

UVM

Object Oriented Programming

Constrained random verification

Proficiency in English

Education

Master’s degree or PhD in Electrical/Computer Engineering

Tools

Python

C++

Verilog

Job description

A leading technology company in Greater London seeks an experienced Design Verification Engineer to join their innovative AMS team. This role entails constructing verification environments, collaborating closely with design engineers, and ensuring high-quality, bug-free designs. Candidates should have a strong background in SystemVerilog and UVM, along with proficiency in Object Oriented Programming. This position offers the chance to work on cutting-edge technologies that impact millions of customers daily.