Low-Latency ASIC Engineer – Physical Design & Verification

Quant Capital; Greater London; On-site; GBP 90,000 - 150,000; Full time

Job summary

Quant Capital is partnering with a leading trading firm to hire ASIC/FPGA engineers for its ultra-low latency hardware team in London. You will own physical design and verification, shaping floorplanning, place-and-route, timing closure and power analysis for demanding trading applications.

The role suits engineers who started in RTL design and moved into physical implementation, with 4+ years in RTL and verification and experience using Synopsys or Cadence tools.

Qualifications

• 4+ years of practical RTL design and verification experience, with ASIC verification focus.
• Read and write RTL; investigate timing or routing issues and contribute to design changes.
• Experience spanning front-end RTL to physical design; deep PD experience preferred.
• Knowledge of Synopsys or Cadence verification tools.
• Familiar with ASICs and FPGAs; formal verification and synthesis experience beneficial.

Responsibilities

• Own physical implementation including floorplanning, place & route, timing closure.
• Perform power analysis and physical verification.
• Read and write RTL; investigate root causes of timing/routing issues and implement design changes.
• Shape verification approach; expand project portfolio across ASICs and FPGAs.
• Develop reusable tools and automation; communicate technical decisions in English.

Skills

RTL design

Physical design

Timing closure

Power analysis

Physical verification

Python

C++

English communication

Tools

Synopsys tools

Cadence tools

Job description

Quant Capital is partnering with a leading trading firm to hire ASIC/FPGA engineers for its ultra-low latency hardware team in London. You will own physical design and verification, shaping floorplanning, place-and-route, timing closure and power analysis for demanding trading applications.

The role suits engineers who started in RTL design and moved into physical implementation, with 4+ years in RTL and verification and experience using Synopsys or Cadence tools.