Senior FPGA Engineer — Ultra-Low Latency Systems Lead

Platform Recruitment; Cambridge; On-site; GBP 90,000 - 130,000; Full time

Job summary

Platform Recruitment in Cambridge is seeking a Senior FPGA Engineer to join a global team developing ultra-low latency technology. You will oversee FPGA system design from architecture to verification, enabling the next generation of infrastructure.

The role requires deep hands-on RTL design experience, SystemVerilog expertise, and proficiency with Vivado or Quartus. You will collaborate across firmware, software, and infrastructure teams to optimise performance and mentor other engineers.

Qualifications

• 7+ years’ FPGA / RTL design experience in timing-critical systems.
• Strong background in SystemVerilog, synthesis, timing closure and verification.
• Hands-on with Vivado / Quartus or equivalent toolchains.
• Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.

Responsibilities

• Architect RTL designs on high-end FPGAs (Xilinx / Intel).
• Perform simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems.
• Lead the definition of micro-architectures and verification environments.
• Driving technical excellence across the FPGA team through mentorship and code reviews.
• Collaborating with firmware, software and infrastructure teams to optimise full-stack performance.

Skills

SystemVerilog

RTL design

Timing analysis

Synthesis

AXI

PCIe

Ethernet

Python

C++

Mentorship

Tools

Vivado

Quartus

Job description

Platform Recruitment in Cambridge is seeking a Senior FPGA Engineer to join a global team developing ultra-low latency technology. You will oversee FPGA system design from architecture to verification, enabling the next generation of infrastructure.

The role requires deep hands-on RTL design experience, SystemVerilog expertise, and proficiency with Vivado or Quartus. You will collaborate across firmware, software, and infrastructure teams to optimise performance and mentor other engineers.