ASIC Engineer

Quant Capital; Greater London; On-site; GBP 90,000 - 150,000; Full time

Job summary

Quant Capital is partnering with a leading trading firm to hire ASIC/FPGA engineers for its ultra-low latency hardware team in London. You will own physical design and verification, shaping floorplanning, place-and-route, timing closure and power analysis for demanding trading applications.

The role suits engineers who started in RTL design and moved into physical implementation, with 4+ years in RTL and verification and experience using Synopsys or Cadence tools.

Qualifications

• 4+ years of practical RTL design and verification experience, with ASIC verification focus.
• Read and write RTL; investigate timing or routing issues and contribute to design changes.
• Experience spanning front-end RTL to physical design; deep PD experience preferred.
• Knowledge of Synopsys or Cadence verification tools.
• Familiar with ASICs and FPGAs; formal verification and synthesis experience beneficial.

Responsibilities

• Own physical implementation including floorplanning, place & route, timing closure.
• Perform power analysis and physical verification.
• Read and write RTL; investigate root causes of timing/routing issues and implement design changes.
• Shape verification approach; expand project portfolio across ASICs and FPGAs.
• Develop reusable tools and automation; communicate technical decisions in English.

Skills

RTL design

Physical design

Timing closure

Power analysis

Physical verification

Python

C++

English communication

Tools

Synopsys tools

Cadence tools

Job description

ASIC Engineers | Physical Design & Verification | Trading Technology

Quant Capital is working with a leading trading firm to hire engineers for its ultra low latency hardware team.

The team develops custom hardware for demanding trading applications, with projects spanning ASIC and FPGA technologies. It's a small group with close links to trading, networking and research infrastructure, so you'll have direct input into design decisions and see how your work is used.

We're recruiting across two distinct profiles. You don't need to meet the requirements for both.

Physical Design Engineer

You'll take ownership of physical implementation, covering floorplanning, place and route, timing closure, power analysis and physical verification. We're looking for 8+ years of hands-on experience, with the breadth to manage the full flow and spot risks before they become expensive problems.

You'll also need to read and write RTL. When a timing or routing problem comes back to the design itself, you should be comfortable investigating the cause and contributing to a design change.

This is particularly relevant to engineers who started in RTL design before moving into physical implementation, or who have covered both in a smaller chip team. Deep PD experience matters, but experience confined entirely to the back end won't be enough.

You'll help shape the verification approach, investigate difficult failures and build confidence in designs before they reach hardware.

We're looking for 4+ years of practical RTL design and verification experience, with a significant focus on ASIC verification using Synopsys or Cadence tools. You should understand the hardware you're testing and be comfortable working with designers to get to the root of a problem.

The project portfolio includes both ASICs and FPGAs. Formal verification, front-end design and synthesis, or physical design experience would strengthen your application, but these are not essential.

The engineering environment

The team takes its development tools seriously. Alongside your hardware expertise, you'll bring programming experience in Python, C++ or another high-level language, and an interest in making the design process more reliable and productive.

You'll have scope to improve tools and automation as part of the engineering work. You should be open to learning unfamiliar approaches and able to explain technical decisions clearly in English.