Lead Analog Layout Engineer – High-Speed AI Interconnects

Kandou AI; Reading; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

Kandou AI is redefining AI hardware with MIMO-over-copper and a scalable, energy‑efficient memory fabric. We seek a Lead Analog Layout Engineer to drive custom analog layout, verification, and integration for high‑speed data links across advanced nodes.

You will collaborate with design teams, interact with customers, and work on packaging interfaces, while leveraging Cadence tools and EDA flows to ensure top‑tier performance and reliability.

Qualifications

• Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.
• Experience in layout of high-speed/frequency circuits like amplifiers, oscillators, PLLs, DLLs and related building blocks.
• Understanding of layout approaches to high-speed circuits, matching constraints, parasitics minimization, power grids and ESD.
• Experience with 28nm, 14/16nm, 7nm processes.
• Proficient with Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, EM, IR drop, ESD modelling.

Responsibilities

• Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip-to-chip communication links (SerDes up to 28Gb/s and memory IO).
• Layout and verification of very high-speed analog circuits.
• Interact with design team to understand requirements and implement solutions.
• Support IP and chip level integration.
• Support customers on requirements and IP delivery.
• Exposure to flip-chip package technologies.

Skills

Analog layout

High-speed circuits

EDA tools

Semiconductor physics

Communication and teamwork

Education

Graduate in E.E.

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS

Parasitics extraction tools

Job description

Kandou AI is redefining AI hardware with MIMO-over-copper and a scalable, energy‑efficient memory fabric. We seek a Lead Analog Layout Engineer to drive custom analog layout, verification, and integration for high‑speed data links across advanced nodes.

You will collaborate with design teams, interact with customers, and work on packaging interfaces, while leveraging Cadence tools and EDA flows to ensure top‑tier performance and reliability.