Senior Analog Design Engineer — High-Speed SerDes

Kandou Bus SA; England; On-site; GBP 70,000 - 100,000; Full time

Job summary

Kandou Bus SA is seeking an Analog Design Engineer to join its EU/CH/UK-focused team. The role centers on designing, modeling, and verifying high-speed Serdes analog blocks and ensuring they meet stringent performance targets.

The candidate will collaborate with architects and multiple teams across the product lifecycle, from design through silicon validation, leveraging Cadence Virtuoso and related tools. Experience with finFET processes is preferred.

Qualifications

• Master's or Ph.D. in Electronics or related field.
• Minimum 5 years of analog design and layout experience in high-speed serial data-link transceivers or RF multi-tone communications.
• Expertise in high-speed circuits (oscillators, PLLs, DLLs, biasing, amplifiers, DAC/ADC).
• Experience with modern semiconductor processes, preferably finFET nodes.
• Experience using Ocean, MDL or equivalent to automate analog design verification is desirable.

Responsibilities

• Design, model, and verify custom analog designs for high-speed Serdes transceivers.
• Design and verify analog circuits following design flows to meet specs.
• Support and interact with customers on requirements and performance results if needed.
• Support analog IP and chip-level integration.
• Collaborate with architects, leads, layout, verification, and silicon validation teams.

Skills

High-speed analog design

DFT/DFM/ESD

Cadence Virtuoso

Communication skills

Design scheduling

Education

Master's or Ph.D. in Electronics

Tools

Cadence Virtuoso

Ocean

MDL

Job description

Kandou Bus SA is seeking an Analog Design Engineer to join its EU/CH/UK-focused team. The role centers on designing, modeling, and verifying high-speed Serdes analog blocks and ensuring they meet stringent performance targets.

The candidate will collaborate with architects and multiple teams across the product lifecycle, from design through silicon validation, leveraging Cadence Virtuoso and related tools. Experience with finFET processes is preferred.