Senior IC Layout Engineer (Hybrid) – High-Speed Analog IP

IC Resources; Cambridge; Hybrid; GBP 90,000 - 120,000; Full time

Benefits offered by this job

Pension

Private medical

Visa sponsorship

Relocation assistance

Job summary

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own the custom layout and verification of analog circuits, blocks, and IP for multi-Gigabit SerDes and memory IO. The role offers hybrid working with 3 days in the office.

You will lead chip layout activities and benefit from opportunities for career progression, with experience in high-speed designs valued. Tools include Cadence Virtuoso, Spectre/HSpice and Calibre across advanced nodes.

Qualifications

• Experience in custom analog layout for multi-Gigabit SerDes or high-frequency circuits.
• Layout approaches and techniques for high-speed circuits, matching constraints and minimisation of parasitics.
• Familiarity with power grids and ESD requirements in semiconductor design.

Responsibilities

• Own the custom layout and verification of analog circuits, blocks, and IP.
• Lead chip layout activities and contribute to career progression and final product realization.

Skills

Analog IC Layout

High-speed design

Layout optimization

Parasitics minimisation

Power grid design

ESD requirements

IP/layout ownership

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS DRC/LVS

Parasitics extraction

EM

IR drop

Job description

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own the custom layout and verification of analog circuits, blocks, and IP for multi-Gigabit SerDes and memory IO. The role offers hybrid working with 3 days in the office.

You will lead chip layout activities and benefit from opportunities for career progression, with experience in high-speed designs valued. Tools include Cadence Virtuoso, Spectre/HSpice and Calibre across advanced nodes.