Front-End Implementation (Synthesis) Engineer

. Apple (UK) Limited; United Kingdom; On-site; GBP 45,000 - 65,000; Full time

Job summary

Apple (UK) Limited is seeking a GPU Front End Implementation engineer to optimise PPA of the netlist and work closely with RTL and Physical design teams to deliver high-quality netlists for partition milestones. The role involves enhancing methodologies and contributing to outstanding GPUs for Apple products.

You will collaborate with IP teams across multiple sites to translate designs into efficient RTL and gate-level implementations, focusing on timing and performance within Apple Silicon.

Qualifications

• BSc in EE is required.
• Proficient in Verilog and SystemVerilog; familiarity with scripting languages.
• Experience with physical synthesis and PPA optimization techniques.

Responsibilities

• Focus on PPA optimisation of the netlist and collaborate with RTL and Physical design teams.
• Deliver key netlist quality milestones for your partition and contribute to improving current methodologies.
• Collaborate with IP teams across sites to deliver high-performance GPUs for Apple Silicon.

Skills

Verilog

SystemVerilog

Scripting languages

PPA optimization

RTL design

Education

BSc in EE

Job description

Imagine working in a team where the only limits are the laws of physics and your imagination.At Apple, phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices.Join the team that optimises and delivers world class GPUs into Apple Silicon. As part of the GPU Front End Implementation team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.

Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.

Minimum Qualifications

• Minimum of BSc in EE.
• Proficient in Verilog and/or System Verilog and scripting languages.
• Experience with physical synthesis, including logic and PPA optimisation techniques.

Preferred Qualifications

• Understanding and application of physical design and static timing analysis principles.
• Familiarity with DFT insertion.
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
• Experience implementing ECO's for functionality and timing.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Experience using logic equivalence tools for RTL and Gate-level designs.
• Collaborate optimally with IP teams spanning multiple sites.