GPU Front-End Architect & RTL Optimizer

Apple Inc.; Greater London; On-site; GBP 65,000 - 90,000; Full time

Job summary

Apple Inc. in London is seeking an RTL engineer to work on PPA optimisation of the netlist for Apple Silicon GPUs. You will collaborate with RTL and Physical design teams to improve netlist quality milestones and push forward advanced GPU products.

The role requires a BSc in EE and experience with Verilog or SystemVerilog and scripting; knowledge of physical synthesis, timing analysis, and DFT is preferred. Apple values inclusive hiring and accessibility.

Qualifications

• BSc in EE required.
• Experience with Verilog or SystemVerilog and scripting.
• Understanding of physical synthesis and PPA optimisation techniques.

Responsibilities

• PPA optimisation of the netlist and collaboration with RTL and Physical design teams.
• Deliver key netlist quality milestones for partitions and improve methodologies.
• Contribute to delivering GPUs for Apple Silicon and engage with IP teams across sites.

Skills

Verilog

SystemVerilog

PPA optimisation

RTL design

Scripting

Education

BSc in EE

Job description

Apple Inc. in London is seeking an RTL engineer to work on PPA optimisation of the netlist for Apple Silicon GPUs. You will collaborate with RTL and Physical design teams to improve netlist quality milestones and push forward advanced GPU products.

The role requires a BSc in EE and experience with Verilog or SystemVerilog and scripting; knowledge of physical synthesis, timing analysis, and DFT is preferred. Apple values inclusive hiring and accessibility.