Early Career - Front-End Implementation Engineer (Synthesis)

Apple; Greater London; On-site; GBP 70,000 - 95,000; Full time

Job summary

Apple in Greater London seeks a hardware engineer to optimize PPA for netlists and work closely with RTL and Physical design teams to deliver high-quality GPU milestones.

The role involves understanding physical synthesis and timing principles, improving methodologies, and collaborating with IP teams across sites. Applicants should align with Apple’s inclusive culture and accessibility commitments.

Qualifications

• BSc in Electrical Engineering (EE) required.
• Experience with Verilog or SystemVerilog and scripting languages.
• Knowledge of physical synthesis and PPA optimization.

Responsibilities

• Responsible for PPA optimisation of the netlist.
• Collaborate with RTL and Physical design teams to deliver milestones.
• Understand and improve current design methodologies for better GPUs.

Skills

Verilog

SystemVerilog

PPA optimization

RTL collaboration

Education

BSc in EE

Tools

DFT tools

STA tools

linting tools

Job description

Summary

Imagine working in a team where the only limits are the laws of physics and your imagination.

At Apple, phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices.

Description

Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.

Minimum Qualifications

• Minimum of BSc in EE.
• Exposure in Verilog and/or System Verilog and scripting languages.
• General understanding of physical synthesis, including logic and PPA optimisation techniques.

Preferred Qualifications

• Understanding and application of physical design and static timing analysis principles.
• Familiarity with DFT insertion.
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Collaborate optimally with IP teams spanning multiple sites.

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Role Number: 200688187-2114